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REVISION HISTORY
SCHEMATICS CONVENTIONS
JUMPER and SOLDERDROP
REV
DATA
NOTE
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm?"
PAGE
REFERENCE
DEFAULT
FUNCTION
D
A
B
2009.07
2009.11
ORIGINAL RELEASED
UPDATED
(2) "DNP" means the component is not populated
by default
3
JP1
JP2
JP3
OPEN
1-2
OPEN
Close to select JTAG boundary scan
Analog reference voltage selection between 3.3V and 2.5V
Close to reinitialize the Flash contents and some of its NVM bits
D
JP4
JP5, JP6, JP7, JP8
OPEN
CLOSE
Close for manufacturing test or fast programming mode
Access for current measurement on each power rail
TEST POINT
4
JP9
JP11
CLOSE
CLOSE
Nand Flash chip select enable
RS485 bus termination enable
TABLE OF CONTENTS
PAGE
3
REFERENCE
TP1, TP2, TP3, TP4
FUNCTION
GND
5
JP10, JP12
JP13
OPEN
CLOSE
RS485 pull resistor selectors
LCD chip select enable
PAGE
1
2
DESCRIPTION
Block Diagram
Reference guide
4
5
TP5
TP6
TP7
UART TXD
UART RXD
LCD backlight driver anode
6
JP14, JP15
JP17, JP19
JP16, JP21
JP18
OPEN
OPEN
OPEN
1-2
Sync close to degrade gain stage on microphone input
Close to mux RIN/LIN into MONO-IN path within audio PA
Close for impedance matching on AD/DA BNC port
ADC input selection between BNC port and potentiometer
C
3
Microcontroller
TP8, TP9
Aux ADC input for TSC
JP20
OPEN
Close to fix in mono speaker mode, no matter stereo plug state
C
4
NAND Flash, RS232, RS485, MCI, JTAG
SD1
OPEN
DAC path isolation on sharing channel
5
6
7
LCD, Touch items
Audio, AD/DA, Power
IO Expansion, USB, ZigBEE, LED, Button
6
TP12
Optional audio PA input
7
SD2
JP22, JP23, JP24
JP25
CLOSE
2-3
CLOSE
Lead PB13 as AUDIO_OUTL channel
DC voltage selection between 3.3V and 5V on PIO expansion ports
Button BP2 disable
PIO MUXING
JP26
JP27
CLOSE
CLOSE
Button BP3 disable
Power consumption measure for ZigBEE module
PIOA
USAGE
PIOA
USAGE
PIOB
USAGE
PIOC
USAGE
PIOC
USAGE
DEFAULT NO POPULATE PARTS
PA0
PA1
TSLIDR_SL_SNS
TSLIDR_SL_SNSK
PA16
PA17
TSC_IRQ/ZB_IRQ0
TSC_BUSY/ZB_IRQ1
PB0
PB1
MIC INPUT
ANA INPUT
PC0
PC1
D0
D1
PC16
PC17
NAND_ALE
NAND_CLE
PAGE
REFERENCE
FUNCTION
B
PA2
TSLIDR_SM_SNS
PA18
ZB_RSTN
PB2
ZB_NPCS2
PC2
D2
PC18
NAND_RDYBSY
3
J1, R1
External clock resource input
B
PA3
PA4
PA5
TSLIDR_SM_SNSK
TSLIDR_SR_SNS
TSLIDR_SR_SNSK
PA19
PA20
PA21
LED_BLUE
LED_GREEN
RXD1
PB3
PB4
PB5
USER_PB1
JTAG
JTAG
PC3
PC4
PC5
D3
D4
D5
PC19
PC20
PC21
REGSEL_LCD
LED_RED(POWER)
USB_CNX
Y1, R3, R7
R6, R8
R9, R10
Backup 12MHz crystal
Isolation between 12MHz clock source and GPIO line
Isolation between 32KHz clock source and GPIO line
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
MCI_CD
CLK_32K
CLK_32K
RX_UART0
TX_UART0
TSC_CS
MISO
MOSI
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
TXD1
COM1EN
RTS1
CTS1
MCI
MCI
MCI
MCI
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
JTAG
JTAG
CLK_12M
CLK_12M
USB_DDM
USB_DDP
ERASE
AUDIO OUT R
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
D6
D7
WR_LCD
NAND_OE
NAND_WE
RD_LCD
USER_PB2
EN_LCD
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
TVALID_SNS
TVALID_SNSK
TUP_SNS
TUP_SNSK
TDWN_SNS
TDWN_SNSK
TLEFT_SNS
TLEFT_SNSK
4
5
R22
R23
R24, R30
R25
D1
R61, R62, RA2, RA3
Optional write protection on NAND flash
Optional pull up for open drain output on equivalent device
Differential impedance matching for RS485 cable
Disconnect RS485 Receive data from PA21
Optional ESD protection for LCD touch panel
Optional databus termination for LCD controller
PA14
PA15
SPCK
ZB_SLPTR
PA30
PA31
MCI
MCI
PB14
AUDIO OUT L
PC14
PC15
NAND_NCS0
NSC1_LCD
PC30
PC31
TRIGHT_SNS
TRIGHT_SNSK
A
A
B
A
REV
INIT EDIT
MODIF.
PP
NL
DES.
26-NOV-09
XX-XXX-XX XXX XX-XXX-XX
DATE VER. DATE
1/1
SAM3S-EK SCALE
Describe
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
REV.
B
SHEET
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